Programmable read only memory

ABSTRACT

A programmable read-only memory (PROM) circuit is provided wherein each one of a plurality of fusible links is coupled between a different row and column conductor of a matrix of row and column conductors and wherein each one of the row conductors is coupled to a corresponding one of a plurality of row driver circuits, each one having an output transistor connected to the corresponding one of the row conductors. Switch means are provided for feeding a first level of base current to the output transistors during the programming mode and for feeding a second, lower level of base current to such output transistors during the read mode.

BACKGROUND OF THE INVENTION

This invention relates generally to programmable read-only memory (PROM)circuitry and, more particularly, to PROM circuitry having relativelylarge memory capacity.

As is known in the art, PROM circuits have a wide range of applicationsin digital computation and processing systems. As is also known in theart, such PROM circuits are typically formed as a single semiconductorintegrated circuit chip. In bipolar PROM circuits, a matrix of rows andcolumns of conductors have memory elements connected between a uniquerow conductor-column conductor combination. Each one of the memoryelements typically includes a diode and serially connected fusible link.During programming, selected ones of the fusible links are blown,creating an open circuit between the previously electrically connectedrow conductor and column conductor connected to such blown fusible link.The resulting pattern of blown and unblown fusible links represents datastored in the PROM. More particularly, a blown fusible link at a"location" defined by the unique row conductor-column conductorpreviously connected to such blown fusible link may represent a logical0 signal stored at such location; whereas an unblown fusible link at asecond address defined by a different row conductor-column conductorcombination may represent a logical 1 signal stored at such secondaddress.

More specifically, in the bipolar PROM circuit referred to above, eachone of the row conductors is coupled to a corresponding row drivercirciut. Each one of such row driver circuits includes an outputtransistor having a collector electrode connected to the row conductorcoupled to such row driver circuit and an emitter electrode connected toa fixed potential, typically ground. When it is desired to fuse one ofthe fusible links coupled to a particular row conductor, base current issupplied to the one of the output transistors having its collectorelectrode connected to it to drive such transistor into saturation.Current is supplied to the one of the column conductors connected to thefusible link desired to be blown. Such current then flows through theselected fusible link, through the collector-emitter electrodes of thesaturated output transistor to ground. Typically, the amount of currentrequired to blow the fusible link is in the order of 25 milliamperes(ma). It is noted that, during the selection of one of the fusiblelinks, the fusible links connected to the unselected row conductors havethe diodes serially connected thereto reverse biased by a relativelyhigh voltage produced at the collector electrodes of the outputtransistors of the unselected row driver circuits. While such voltagereverse biases these diodes, leakage current (typically 1.5 microampereper diode) does pass through such diodes and through the selected,saturated output transistor to ground potential. While in PROM circuitshaving a relatively small number of memory elements, typically less than8 K, such leakage current is insignificant, in PROM circuits having,say, 16 K memory elements, the total leakage current passing through thesaturated output transistor is in the same order of magnitude as thecurrent needed to fuse or blow the selected fusible link. Therefore, theamount of current which such output transistor must sink issignificantly increased as the memory capacity of the PROM is increased.One way to provide an output transistor which is able to sink thisadditional current is to increase the area required to form suchtransistor; however, such approach has the concommitant effect ofreducing the amount of available area on the surface of thesemiconductor chip.

SUMMARY OF THE INVENTION

In accordance with the present invention, a programmable read-onlymemory (PROM) circuit is provided wherein each one of a plurality offusible links is coupled between a different row and column conductor ofa matrix of row and column conductors and wherein each one of the rowconductors is coupled to a corresponding one of a plurality of rowdriver circuits, each one having an output transistor connected to thecorresponding one of the row conductors. Switch means are provided forfeeding a first level of base current to the output transistors duringthe programming mode and for feeding a second lower level of basecurrent to such output transistors during the read mode.

With such arrangement, the output transistors have decreased forced betaand are thereby able to sink both current required to blow a fusiblelink and additional leakage current passing through diodes seriallyconnected to unselected fusible links during the program mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and other features of the invention are explainedin more detail in the following description taken in conjunction withthe accompanying drawing which shows a schematic diagram of aprogrammable read-only memory (PROM) circuit according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the single FIGURE, a programmable read-only memory(PROM) circuit 10, here a 16 K PROM, is shown to include a memory array12, here arranged to store 16,384 bits of information arranged as 2048eight-bit digital words. The memory array 12 thus has eight sections13a-13h, each one of such sections 13a-13h being arranged to store adifferent one of the eight bits of the 2048 digital words. Thus, whileeach one of the sections 13a-13h includes row conductors 14₁ -14₁₂₈,sections 13a through 13h include column conductors 16_(1a) -16_(16a)through 16_(1h) -16_(16h), respectively, as indicated. Each one of aplurality of, here 16,384, memory elements 18 is coupled between aunique one of the row conductors 14₁ -14₁₂₈ and column conductors16_(1a) -16_(16h), as indicated, the memory element labeled 18a beingshown connected between row conductor 14₁ and column conductor 16_(1a) .Each one of the memory elements 18 includes a diode 20, here a Schottkydiode, and a serially connected fusible link 22, as shown.

An X decoder section 24 is connected to the row conductors 14₁ -14₁₂₈,as shown, such X decoder section 24 being coupled to terminals A₀ -A₆through conventional X address inverter section 30. As will be describedin detail hereinafter, terminals A₀ -A₆ are fed by 7 bits of an 11-bitaddress word, the remaining four bits of such address word being fed toterminals A₇ -A₁₀. Suffice it to say here, however, that the logicsignals fed to terminals A₀ -A₆ provide seven bits of the eleven bitsused to address the 2048 words stored in the PROM 10. As mentioned, theX address inverter section 30 is of any conventional design and, inresponse to the logic signals A₀ -A₆ fed respectively to terminals A₀-A₆ produces true signals A₀ '-A₆ ' and complementary signals A₀ '-A₆ 'respectively on lines A₀ '-A₆ '. The signals on lines A₀ '-A₆ ' and A₀'-A₆ ' are fed to the X decoder section 24 as shown.

The X decoder section 24 includes a plurality of, here 128, row drivercircuits 32₁ -32₁₂₈, as shown. Each one of such row driver circuits 32₁-32₁₂₈ includes an input transistor 33₁ -33₁₂₈ having base electrodescoupled to a +V_(cc) supply, here +5 volts, through resistors 34₁-34₁₂₈, respectively, as indicated. The seven emitter electrodes of eachone of the input Schottky transistors 33₁ -33₁₂₈ are coupled to selectedones of the lines A₀ '-A₆ ' and A₀ '-A₆ ' in a conventional manner; herelines A₀ '-A₆ ' are coupled to the seven emitter electrodes oftransistor 33₁ and lines A₀ '-A₆ ' are coupled to the seven emitterelectrodes of transistor 33₁₂₈, as shown. The collector electrodes oftransistors 33₁ -33₁₂₈ are coupled to the base electrodes of couplingSchottky transistors 35₁ -35₁₂₈, respectively as indicated. Thecollector electrodes of transistors 35₁ -35₁₂₈ are fed to a power sourceterminal 36 through resistors 37₁ -37₁₂₈, respectively, as indicated. Aswill be described hereinafter, during the program mode, the voltage atpower source terminal 36 is relatively high, here +10 volts, whereasduring the read mode the voltage at the power source terminal 36 is of alower voltage, here approximately V_(cc) (i.e., 5 volts). With sucharrangement, during the program mode, i.e., with the higher voltagecoupled to power source terminal 36, a larger current flows from suchpower source terminal 36 through the collector-emitter electrodes of aselected one of the coupling transistors 35₁ -35₁₂₈ to the baseelectrode of the one of a plurality of output transistors 38₁ -38₁₂₈coupled to the emitter electrode of the selected one of the couplingtransistors 35₁ -35₁₂₈. In this way the one of the output transistors38₁ -38₁₂₈ coupled to the selected one of the coupling transistors 35₁-35₁₂₈ operates at a relatively low forced beta during the program modeand is able to sink, when in saturation, both the current required tofuse a selected one of the fusible links 22 and the total reverse biasor leakage current flowing through the diodes 20 serially connected tothe unselected fusible links. Completing the description of the rowdriver circuits 32₁ -32₁₂₈, the base electrodes of output transistor 38₁-38₁₂₈ are coupled to ground through resistors 39₁ -39₁₂₈, respectively,as shown; the collector electrodes of coupling transistors 35₁ -35₁₂₈are coupled to the collector electrodes of output transistors 38₁-38₁₂₈, respectively as shown, through resistors 40₁ -40₁₂₈ and seriallyconnected Schottky diodes 41₁ -41₁₂₈, respectively, as indicated. Thecollector electrodes of output transistors 38₁ -38₁₂₈ are connected torow conductors 14₁ -14₁₂₈, respectively as indicated; and the emitterelectrodes of output transistors 31₁ -38₁₂₈ are connected to ground,respectively as shown.

The column conductors 16_(1a) -16_(16a) through 16_(1h) -16_(16h) arefed to Y decoders 50_(a) -50_(h), respectively as shown. Thus,considering section 13a of memory array 12, column conductors 16_(1a)-16_(16a) are fed to Y decoder 50a through the emitter electrodes oftransistors 52_(1a) -52_(16a), respectively as indicated. To put it moregenerally, the column conductors of sections 13a-13h are coupled to Ydecoders 50a-50h respectively through sets of transistors 52_(1a)-52_(16a) through 52_(1h) -52_(16h), respectively as indicated. Each oneof the Y decoders 50a-50h is identical in construction and here is aconventional diode matrix fed by control signals supplied by Y addressinverter section 54 and a +V_(cc) supply, as indicated. The controlsignals produced by the Y address inverter section 54 (which isequivalent to the X address inverter section 30 discussed above) aretrue and complement signals of the logic signals fed to terminals A₇-A₁₀. That is, the logic signals A₇ -A₁₀ fed to terminals A₇ -A₁₀ supplyfour of the 11-bit address signals for the 2048 words stored in the PROM(the remaining 7 bits being fed to terminals A₀ -A₆ as described above).Thus, the Y address inverter section 54 produces true signals A₇ '-A₁₀ 'and complement signals A₇ '-A₁₀ ', such signals providing the controlsignals for each one of the Y decoders 50a-50h. Thus in response tologic signals fed to terminals A₇ -A₁₀, base current flows from the+V_(cc) source, to a selected one of the transistors 52_(1a) -52_(16a)coupled to the Y decoder 50a, thereby selecting the one of the columnconductors 16_(1a) -16_(16a) connected to the emitter electrode of theselected one of the transistors 52_(1a) -52_(16a). More generally, thecontrol signals produced by Y address inverter section 54 select one ofthe column conductors in each one of the sections 13a-13h of the memoryarray 12. Transistors 52_(1a) -52_(16a) through transistors 52_(1h)-52_(16h) have collector electrodes connected together to teminals57a-57h, respectively as shown. Terminals 57a-57h are coupled to outputbuffers 58a-58h, respectively as shown. Thus, in response to the controlsignals produced by Y address inverter section 54 of a selected one ofthe column conductors of each of the sections 13a-13h of memory array 12is coupled to a corresponding one of the output buffers 58a-58h,respectively as indicated. Each one of the output buffers 58a-58h iscoupled to a corresponding one of output terminals O₀ -O₇, respectivelyas shown. As will be described, during the program mode current fed toone of the output terminals O₀ -O₇ passes through one of the fusiblelinks 22 in the one of the sections 13a-13h of the memory array 12, suchfusible link being selected by the address signals A₀ -A₁₀ ; whereasduring the read mode each one of the output terminals O₀ -O₇ produces alogic signal representative of the eight bits of the one of the 2048words stored in the PROM 10 and selected by the address signals A₀ -A₁₀.

The PROM 10 includes a PROM program enable section 60. Such section 60is coupled to a terminal E, as shown. More particularly, terminal E iscoupled to the base electrode of a P-N-P transistor 61 and to the anodeof a zener diode 73 as shown. Here, zener diode 73 has a breakdownvoltage of 7 volts. The cathode of zener diode 73 is connected to aterminal 75, as shown. The transistor 61 is a multiple emittertransistor having one emitter connected to the +V_(cc) supply through aresistor 63 as shown and to the base electrode of Schottky transistor64, through a Schottky diode 62, as shown. The other emitter oftransistor 61 is directly connected to the base electrode of transistor64, as shown. The emitter of transistor 64 is coupled to the base of thetransistor 65 and to ground through resistor 66, as shown. The emitterof transistor 65 is connected to ground and the collector is connectedto: the collector of transistor 64 through resistor 68 and the +V_(cc)supply through resistor 69, and the base of transistor 67, as shown. Theemitter of transistor 67 is connected through diode 107 to line E and toits collector through resistor 71, as shown.

When the signal fed to terminal E is a relatively high positive voltage,here +33 volts, the PROM 10 is placed in the program mode, and when thesignal fed to terminal E is relatively low, here approximately +0.3volts, the then programmed PROM 10 is placed in the read mode. Moreparticularly, when the +33 volts is fed to terminal E, transistor 61 isturned "off", placing transistors 64, 65 and 67 "on" so that the voltageon line E goes "low". Also such +33 volts causes zener diode 73 to breakdown, producing a +25 volt potential at terminal 75. Terminal 75 is fedto an X decoder power switch 70. Such switch 70 includes a voltagedivider network made up of resistors 74, 76, zener diode 78, transistors80, 82 and resistor 84, connected as shown to produce, in response tothe +25 volt potential at terminal 75, a voltage at power sourceterminal 36 greater than +V_(cc) ; here such switch 70 produces avoltage of +10 volts at terminal 36 in response to the +25 volts atterminal 75 (i.e., switch 70 produces +10 volts at power source terminal36 when a program enable signal (i.e., +33 volts) is fed to terminal E).Conversely, when in the read mode (i.e., when the voltage at terminal Eis low) the zener diode 73 does not break down and terminal 75 is openso that the +V_(cc) source is coupled to power source terminal 36through Schottky diode 83, as shown. Therefore, during the program mode,the output transistors 38₁ -38₁₂₈ of X decoder section 24 are supplied agreater base current from the +10 volts at terminal 36 than during theread mode when approximately 5 volts is fed to terminal 36. The reasonfor changing the voltage at terminal 36, and hence the base current tooutput transistors 38₁ -38₁₂₈ depending on whether the PROM 10 is in theread or program mode, will be discussed in further detail later. Sufficeit to say here, however, that by supplying the higher voltage to therow, or X, driver circuits 32₁ -32₁₂₈ during the program mode willdecrease the forced beta of the output transistors 38₁ -38₁₂₈, allowingsuch output transistors 38₁ -38₁₂₈ to sink not only the current requiredto blow a selected one of the fusible links 22 but also to sink leakagecurrent passing to output transistors from diodes 20 connected tounselected fusible links.

Each one of the output buffers 58a-58h is identical in construction,buffer memory 58a being shown in detail to include transistors 96, 98,99, 100 and 102, as shown. The base electrode of transistor 96 iscoupled to line E through Schottky diode 90 and diode 92 and to terminal57a through resistor 104 and Schottky diode 106. The junction 105 ofresistor 104 and Schottky diode 106 is coupled to a +V_(cc) throughresistor 108 and to the collector of transistor 96 through a Schottkydiode 110, as shown. The collector of transistor 96 is connected to+V_(cc) through resistor 112 and to the base of transistor 98 throughresistor 114 and Schottky diode 116. The base of transistor 98 isconnected to its emitter through resistor 118 and its emitter isconnected: to ground through resistor 120; to the collector oftransistor 99 through a resistor 134; to the base of transistor 99through a resistor 122; and to the base of transistor 107, as shown. Thecollector of transistor 98 is connected to line E through Schottky diode94, to + V_(cc) through resistor 124, and to the base of transistor 102,as shown. The collector of transistor 102 is connected to +V_(cc)through resistor 126 and the emitter is connected to terminal O₀ and tothe collectors of transistors 128, 130 through a Schottky diode 132 asshown. Terminal O₀ is connected to the collector of transistor 107. Theemitter of transistor 107 is grounded and the base is connected to theemitter of transistor 98. The emitter of transistor 99 is connected toground as shown. Terminal 75 of the PROM program enable section 60 iscoupled to the base electrode of transistor 130 through a resistor 136.The base electrode of transistor 130 is connected to the base oftransistor 138. The emitter of transistor 138 is connected to theemitter of transistor 130 and the base of transistor 128, as shown. Thecollector of transistor 138 is grounded. The transistors 128, 130 form aDarlington pair, the emitter of transistor 128 being connected toterminal 57a, as shown.

Continuing in the operation of the PROM 10, then, during the programmode line E is low for reasons set forth above. In response to the lowvoltage on line E diodes 90, 92, and 94 are forward biased placingtransistors 96, 98, 99, 100 and 102 in an "off" or non-conductingcondition. Further, diode 106 is reverse biased. Thus, when it isdesired to program the memory elements 18 in section 13a of the memoryarray 12, a power supply (not shown) is connected to the output terminalO₀ and current flows from such supply through the collector electrodesof Darlington connected transistors 130, 128 (such transistors beingbiased "on" by the high +25 volts at terminal 75) to the collectorelectrode and emitter electrode of the one of the transistors 52_(1a)-52_(16a) selected by the signals on lines A₇ -A₁₀, through the one ofthe column conductors 16_(1a) -16_(16a) connected to such selected oneof the transistors 52_(1a) -52_(16a) through the one of the fusiblelinks 22 connected between such selected one of the column conductors16_(1a) -16_(16a) and one of the row conductors 14₁ -14₁₂₈ selected bythe signals at terminals A₀ -A₆. Thus, current flows through suchselected one of the fusible links 22 connected to the one of theselected row conductors 14₁ -14₁₂₈ to ground through thecollector-emitter electrode of one of the output transistors 38₁ -38₁₂₈connected to such selected one of the row conductors 14₁ -14₁₂₈. Forexample, consider the signals on lines A₀ -A₆ as 0000000: high signalsare produced on each of the seven emitter electrodes of transistor 33₁,causing current to flow through resistor 34₁ and the collector oftransistor 33₁ to turn "on" transistors 35₁ and 38₁, while transistors33.sub. 2 -33₁₂₈ have at least one of their emitters at a low voltage sothat transistors 38₂ -38₁₂₈ are hence "off" or non-conducting. Iffollows that the voltage on line 14₁ is "low" and the voltage on lines14₂ -14₁₂₈ are "high" (i.e., about 10 volts). Consider also that thesignals on lines A₇ -A₁₀ enable Y decoder 50a to turn on transistor52_(1a), thus selecting memory element 18a (i.e., the memory elementconnected between row conductor 14₁ and column conductor 16_(1a)).Current passes from the source (not shown) connected to terminal O₀through the fusible link 22 of memory element 18a of sufficient level toblow such link 22. The path of this current is shown by the solid arrow150. It is noted that transistor 38₁ not only must sink this current,typically 25 ma, but must also sink leakage current, indicated by thedotted arrows 152, passing through the reverse biased diodes 20 of theunselected memory elements 18. While each diode has only about 1.5microamperes reverse bias current, here there are in excess of 15,000such diodes so that the total leakage current which must pass throughtransistor 38₁ is 24 ma. It is noted that such transistor 38₁ is able tosink this large amount of current because it has a lower forced beta asa result of a relatively large base current supplied from a higher, here+10 volt, supply produced at terminal 36 by the X decoder power supplyswitch 70.

After the section 13a of the memory array 12 is programmed, sections13b-13h become sequentially programmed in like manner by connecting thesupply (not shown) previously coupled to terminal O₀ sequentially toterminals O₁ -O₇ respectively.

During the read mode, a low voltage, here +0.3 volts, is fed to terminalE. In response to such low voltage signal the X decoder power supplyswitch 70 couples the +V_(cc) supply to terminal 36, such +V_(cc) supplynow providing the source for the row, or X, driver circuits 32₁ -32₁₂₈.Word address signals are fed to terminals A₀ -A₁₁, thereby selecting oneof the row conductors 14₁ -14₁₂₈ as described for the program mode andone of the column conductors in each one of the sections 13a-13h,respectively. It is noted that in response to the low voltage onterminal E transistor 61 turns "on" and transistors 64 and 65 turn "off"placing a "high" voltage (i.e., V_(cc)) on line E reverse biasing diodes90, 92 and 94. Thus, for example, if the fusible link 22 of memoryelement 18a had not been blown and such memory element 18a is nowselected during the subsequent read mode, the low voltage on line 14₁resulting from transistor 38₁ being turned "on", would be coupled tocolumn conductor 16_(1a) and to the collector of transistor 52_(1a) toterminal 57a and to the base of transistor 96 through forward biaseddiode 106. This low voltage at the base of transistor 96 placestransistor 100 in an "off" state so that the voltage at terminal O₀ isV_(cc) or high, indicating that (unblown) memory element 18a representsor stores a logical 1 signal. (It is noted that, during the read mode,the voltage at terminal 75 is "open" and, hence, transistors 128, 130are disabled.) If, on the other hand, the fusible link 22 of memoryelement 18a had been blown (i.e., was open circuit), then, during thesubsequent read mode the voltage at the base of transistor 96 would behigh from V_(cc), resistors 108, diode 116, resistor 114, resistor 118,and resistor 120, turning transistor 96 and transistors 98, 99 and 100to conduction so that the voltage at terminal O₀ would be "low,"indicating that (blown) memory element 18a represents or stores alogical 0. Output buffers 58b-58h operate simultaneously in like manner,thereby enabling the PROM to read the 8-bit contents of the word storedat the location addressed by the signals on lines A₀ -A₁₁.

Having described a preferred embodiment of this invention, it is nowevident that other embodiments incorporating its concepts may be used.It is felt, therefore, that this invention should not be restricted tosuch preferred embodiment but rather should be limited only the spiritand scope of the appended claims.

What is claimed is:
 1. A programmable read-only memory circuitcomprising:(a) a memory array comprising a plurality of addressableprogrammable memory elements; (b) address circuitry for addressing theprogrammable memory elements of the memory array, such address circuitryhaving a plurality of output transistors coupled to different ones ofthe programmable memory elements and including means for driving aselected one of the output transistors into saturation to address aportion of the array; and (c) means including a program enable circuitresponsive to a program enable signal and a read mode signal forsupplying a first level of base electrode current to said selected,saturated output transistor during a program mode and a second,different level of base electrode current to said selected, saturatedoutput transistor during a read mode.
 2. The circuit recited in claim 1wherein such one of the addressable programmable memory elementsincludes a diode and a serially connected fusible link.
 3. The circuitrecited in claim 2 wherein each one of the output transistors has itsemitter and collector electrodes serially coupled to a corresponding rowof the fusible links.
 4. A programmable read-only memory circuitcomprising:(a) a memory array comprising a plurality of addressablememory elements arranged in a matrix of rows and columns, each one ofsuch elements including a fusible link and a serially connected diode;(b) address circuitry for addressing the memory elements, such addresscircuitry having a plurality of output transistors each one having acollector electrode coupled to a different one of the rows ofprogrammable memory elements including means for driving a selected oneof the output transistors into saturation to address a portion of thearray; (c) means including a program enable circuit responsive to aprogram enable signal and a read mode signal for supplying a first levelof base electrode current to said selected, saturated output transistorduring a program mode and a second, lower level of base electrodecurrent to said selected, saturated output transistor during a readmode.
 5. A programmable read-only memory circuit comprising:(a) a memoryarray comprising a plurality of addressable programmable memory elementsarranged in a matrix of rows and columns; (b) address circuitry foraddressing one of the programmable memory elements of the memory arrayselectively in response to row and column addessing signals, suchaddressing circuitry having a first plurality of output transistors foraddressing the elements in the rows of the array and a second pluralityof output transistors for addressing the elements in the columns of thearray; (c) output circuitry coupled between the second one of theplurality of output transistors and an output terminal for coupling asource of programming current fed to the output terminal through one ofthe second plurality of output transistors to the one of the memoryelements selected in accordance with the row and column addressingsignals during a program mode to program such selected element and forcoupling a signal indicative of a logic state represented by one of theprogrammed memory elements selected in accordance with the row andcolumn addressing signals through one of the selected one of the secondplurality of output transistors to said output terminal during a readmode; and (d) means including a program enable circuit responsive to aprogram enable signal and a read mode signal for supplying a first levelof current to a base electrode of one of the first plurality of outputtransistors selected in accordance with row addressing signals duringthe program mode and a second, different level of current to the baseelectrode of one of the first plurality of output transistors selectedin accordance with the row addressing signals during the read mode.
 6. Aprogrammable read-only memory comprising:(a) a memory array comprising aplurality of addressable programmable memory elements arranged in amatrix of rows and columns, each one of such memory elements including afusible link and a serially connected diode; (b) addressing circuitryfor addressing a selected one of the programmable memory elements of thememory array, such one of the programmable memory elements beingselected in accordance with row and column addressing signals, suchaddressing circuitry having a plurality of output transistors coupled todifferent ones of the rows of the programmable memory elements and meansfor driving a selected one of such output transistors into saturation toaddress one of the rows of elements; (c) means including a programenable circuit responsive to a program enable signal and a read modesignal for supplying a first level of base electrode current to theselected saturated one of the output transistors during a program modeand a second, lower level of current to the base electrode of theselected saturated one of the output transistors during a read mode,such first level of current decreasing the forced beta of the selectedsaturated one of the output transistors during the program mode to allowsuch selected saturated one of the output transistors to passtherethrough current required to open the fusible link of the selectedone of the memory elements and, additionally, leakage current passingthrough reverse biased diodes of other ones of the memory elements.